An example of an unconstrained type is std_logic_vector.The length of the vector gets declared when the type is used, and is not a … Still I would not mind to avoid it, it looks a tad hacky...I have discussed this over Xilinx SR and it turned out that I have forgot to enable VHDL 2008 for all files, now it works.

A typical examples is std_ulogic_vector: type std_ulogic_vector is array (natural range <>) of std_ulogic; VHDL does not put any restrictions on the index set of arrays, as long it is a discrete range of values. tuser of undefined length.

The advantage of unconstrained arrays is the possibility to concatenate objects of different lengths, for example, because they are still of the same data type. Mobile friendly. tuser

tuser We can collect any data type object in an array type, many of the predefined VHDL data types are defined as an … VHDL 2008 - unconstrained array of record containi...

Unconstrained ranges .
But Vivado is reluctant to sythesise it... With this error:Which indicate it does actually accept the syntax of record constraint (as you would expect from VHDL 2008 sythesiser)Is this supposed to be un-supported in Vivado Synthesis?If it is indeed unsupported what would you suggest to use intead of unconstrained arrays and records?The thing is that my design quite often changes the bit size of the stream.. An object (signal, variable or constant) of an unconstrained array type must have it's index type range defined when it is declared. So using generic packages would be quite inelegant (especially this register is nice example when in one file you have the bus with different sizes of data bus)So far I have used one dimensional slv without records with manual indexing using functions/procedures, but that is quite messy to maintain...I have discussed this over Xilinx SR and it turned out that I have forgot to enable VHDL 2008 for all files, now it works.What is interesting is, that it actually synthesise if I do following:So that means that the array of records with unconstrained array is actually supported, but the direct constraint syntax is not.Any ideas how to define it less elaboratively?

String, bit_vector and std_logic_vector are defined in this way.

Although it's not a big deal to define top-level like this.. Re: VHDL: How to create type for unconstrained array for entity port You cannot do this with VHDL '93, as types need to constrained in all dimensions other than the highest, so you are limited to declaring the constant and type in a package, and you cannot use a generic for the word width, like dpaul has demostrated Auto-suggest helps you quickly narrow down your search results by suggesting possible matches as you type.

What is an array. I am experimenting to synthesise some VHDL 2008 code in Vivado 2016.3 (the same situation is in 2016.4)The idea is to be able to have unconstrained array in record and at the same time have unconstrained array of these records.And finally test_entity_top.vhd which basically constraints the sizes for synthesis:This all nicely compiles in ModelSim. An array type definition can be unconstrained, i.e. as shown below.

In VHDL such kind of structure is defined “array“.

tuser VHDL 2008 - unconstrained array of record containing unconstrained array) VHDL online reference guide, vhdl definitions, syntax and examples. Array. VHDL 2008: Unconstrained fields in records . an unconstrained array of a std_logic_vector(31 downto 0). VHDL has the concept of unconstrained data types, which means that the range of an array or vector is not declared in the type.The range must be declared when an instance of the type is created. Examples of unconstrained types: Real_Matrix is when an unconstrained type and an object of this type is declared (Real_Matrix_Object) it is restricted to 8 elements.
Proper use of newlines (and Sigasi Studio’s formatting – try Records in VHDL: Initialization and Constraining unconstrained fields-- Declare a constant: declare the value of each field-- Not recommended: positional binding for record constants-- initialize recarr1(1) from the existing constant-- initialize the rest of the array with the value of zero_rec1-- others: initialize all bits of the std_logic_vector-- The length of the fields is undeclared at this point In any software programming language, when we need to deal with a collection of elements of the same type we can take advantage of the dedicated data structures provided by the language. tuser VHDL also allows you to define unconstrained arrays, which are array declarations where the type of the index values is specified, but not the bounds. I am experimenting to synthesise some VHDL 2008 code in Vivado 2016.3 (the same situation is in 2016.4) The idea is to be able to have unconstrained array in record and at the same time have unconstrained array of these records.

This would not be allowed if each array length was declared as separate data type. And like you said, a unconstrained 2 dimensional array of std_logic is allowed.

Even a record containing an unconstrained array of records is possible,
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